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Books
| B1 | S. Pasricha, and N. Dutt. “On-Chip Communication Architectures”, Morgan Kauffman, ISBN 978-0-12-373892-9, Apr 2008 [link] |
Books Chapters
| BC5 | S. Pasricha, “Network and Communication Signals for Indoor Navigation”, to appear, 21st Century PNT, Wiley Publishers, 2017. |
| BC4 | S. Pasricha, S. V. R. Chittamuru, I. Thakkar, “’Enhancing Process Variation Resilience in Photonic NoC Architectures’”, to appear, Optical Interconnects for Computer Systems, River Publishers, 2016. |
| BC3 | N. Kapadia, S. Pasricha, “Robust Application Scheduling with Adaptive Parallelism in Dark-Silicon Constrained Multicore Systems”, to appear, The Dark Side of Silicon (Computing in the Dark Silicon Era), Springer, 2016. |
| BC2 | S. Pasricha, Y. Zou, “Hybrid Partially Adaptive Fault Tolerant Routing for 3D Networks-on-Chip”, Embedded Systems: Hardware, Design, and Implementation, (ed K. Iniewski), John Wiley & Sons, Inc., Hoboken, NJ, USA. doi: 10.1002/9781118468654.ch10, Nov 2012. |
| BC1 | S. Pasricha, N. Dutt, “On-chip optical ring bus communication architecture for heterogeneous MPSoC”, Integrated Optical Interconnect Architectures for Embedded Systems, I. O’Connor and G. Nicolescu (eds.), DOI 10.1007/978-1-4419-6193-8_5, Nov 2012. |
Peer Reviewed Journal Articles
| J43 | Y. Biran, S. Pasricha, G. Collins, J. Dubow, “Clean Energy Use for Cloud Computing Federation Workloads”, to appear, Advances in Science, Technology and Engineering Systems Journal, 2017. |
| J42 | A. Khune, S. Pasricha, “Mobile Network-Aware Middleware Framework for Energy Efficient Cloud Offloading of Smartphone Applications”, to appear, IEEE Consumer Electronics, 2017. |
| J41 | H. Mahajan, T. Bradley, S. Pasricha, “Application of systems theoretic process analysis to a lane keeping assist system”, to appear, Journal of Reliability Engineering and System Safety, vol. 167, pp. 177-183, Nov. 2017. |
| J40 | C. Langlois, S. Tiku, S. Pasricha, “Indoor localization with smartphones”, to appear, IEEE Consumer Electronics, 2017. |
| J39 | D. Machovec, B. Khemka, N. Kumbhare, S. Pasricha, A. A. Maciejewski, H. J. Siegel, A. Akoglu, G. A. Koenig, S. Hariri, C. Tunc, M. Wright, M. Hilton, R. Rambharos, C. Blandin, F. Fargo, A. Louri, N. Imam, “Utility-Based Resource Management in an Oversubscribed Energy-Constrained Heterogeneous Environment Executing Parallel Applications”, to appear, Journal of Parallel Computing (PARCO), 2017. |
| J38 | Y. Raparti, N. Kapadia, S. Pasricha, “ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-based Chip Multiprocessors”, to appear, IEEE Transactions on Multi-Scale Computing Systems (IEEE TMSCS), 2017. |
| J37 | M. Oxley, E. Jonardi, S. Pasricha, H. J. Siegel, T. Maciejewski, P. J. Burns, and G. Koenig “Rate-based Thermal, Power, and Co-location Aware Resource Management for Heterogeneous Data Centers”, accepted for publication, Journal of Parallel and Distributed Computing (JPDC), 2017. |
| J36 | S. V. R. Chittamuru, S. Desai, S. Pasricha, “SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast Enabled Channel Sharing for Multicore Architectures”, accepted for publication, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2017. |
| J35 | D. Dauwe, E. Jonardi, R. Friese, S. Pasricha, A. A. Maciejewski, D. Bader, H.J. Siegel, “HPC Node Performance and Energy Modeling Under the Uncertainty of Application Co-Location”, Journal of Supercomputing, Vol. 72, No. 12, pp. 4771-4809, Nov. 2016. |
| J34 | N. Kapadia, S. Pasricha, “A Runtime Framework for Robust Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 2, pp. 534-546, Aug. 2016. |
| J33 | S. Bahirat, S. Pasricha, “A Software Framework for Rapid Application-Specific Hybrid Photonic Network-on-Chip Synthesis”, Electronics, Special Issue on Rapid System Design with Dedicated Architectures and Specific Software Tools, 5(2), 21, 2016. |
| J32 | N. Kapadia, S. Pasricha, “A System-Level Co-Synthesis Framework for Power Delivery and On-chip Data Networks in Application-Specific 3D ICs”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.24, no.1, pp.3-16, Jan. 2016. |
| J31 | Y. Xiang, S. Pasricha, “Soft and Hard Reliability-Aware Scheduling for Multicore Embedded Systems with Energy Harvesting”, IEEE Transactions on Multi-Scale Computing Systems (IEEE TMSCS), Oct-Dec, vol. 1, no. 4, pp. 220-235, 2015. |
| J30 | Y. Xiang, S. Pasricha, “Run-Time Management for Multi-Core Embedded Systems with Energy Harvesting”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.23, no.12, pp.2876-2889, Dec. 2015. |
| J29 | M. Oxley, S. Pasricha, A. A. Maciejewski, H. J. Siegel, J. Apodaca, D. Young, L. Briceno, J. Smith, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou,, “Makespan and Energy Robust Stochastic Static Resource Allocation of Bags-of-Tasks to a Heterogeneous Computing System”, IEEE Transactions on Parallel and Distributed Systems, vol.26, no.10, pp. 2791-2805, Oct. 2015. |
| J28 | I. Thakkar, S. Pasricha, “3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead”, IEEE Transactions on Multi-Scale Computing Systems (TMSCS), vol.1, no.3, pp.168-184, Sep. 2015. |
| J27 | I. Thakkar, S. Pasricha, “3D-WiRED: A Novel Wide I/O DRAM with Energy-Efficient 3D Bank Organization”, IEEE Design and Test (IEEE D&T), vol.32, no.4, pp.71-80, Aug. 2015. |
| J26 | B. Donohoo, C. Ohlsen, S. Pasricha, “A Middleware Framework for Application-aware and User-specific Energy Optimization in Smart Mobile Devices”, Journal of Pervasive and Mobile Computing, vol. 20, pp. 47-63, Jul 2015. |
| J25 | S. V. R. Chittamuru, S. Pasricha, “Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures”, IEEE Design and Test (IEEE D&T), vol.32, no.3, pp.29-39, June 2015. |
| J24 | B. Khemka, R. Friese, S. Pasricha, A. A. Maciejewski, H. J. Siegel, G. A. Koenig, S. Powers, M. Hilton, R. Rambharos, and S. Poole, “Utility Maximizing Dynamic Resource Management in an Oversubscribed Energy-Constrained Heterogeneous Computing System”, Journal of Sustainable Computing: Informatics and Systems, 2014, Volume 5, pp. 14–30, March 2015. |
| J23 | A. M. Al-Qawasmeh, S. Pasricha, A. M. Maciejewski, H. J. Siegel, “Power and Thermal-Aware Workload Allocation in Heterogeneous Data Centers”, IEEE Transactions on Computers, vol. 64, Iss 02, pp. 477-491, Feb 2015. |
| J22 | Y. Xu, S. Pasricha, “Silicon Nanophotonics for Future Multicore Architectures: Opportunities and Challenges”, IEEE Design and Test (D&T), Special Issue on Silicon Nanophotonics for Future Multicore Architectures, Sep/Oct, pp. 9-17, 2014. |
| J21 | B. Donohoo, C. Ohlsen, S. Pasricha, C. Anderson, Y. Xiang, “Context-Aware Energy Enhancements for Smart Mobile Devices”, IEEE Transactions on Mobile Computing (TMC), Vol 13, No. 8, pp. 1720-1732, Aug 2014. |
| J20 | S. Bahirat, S. Pasricha, “METEOR: Hybrid Photonic Ring-Mesh Network-on-Chip for Multicore Architectures”, ACM Transactions on Embedded Computing Systems (TECS), 13(3):116:1-116:33, Mar 2014. |
| J19 | L. Bathen, Y. Ahn, S. Pasricha, N. Dutt, “MultiMaKe: Chip-Multiprocessor Driven Memory-aware Kernel Pipelining”, ACM Transactions on Embedded Computing Systems (TECS), 12(1), Mar 2013. |
| J18 | Y. Zou, Y. Xiang, S. Pasricha, “Characterizing Vulnerability of Network Interfaces in Embedded Chip Multiprocessors”, IEEE Embedded System Letters, 4(2), Jun 2012. |
| J17 | D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Deadline and Energy Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, Journal of Supercomputing, 2012. |
| J16 | N. Kapadia, S. Pasricha, “A Framework for Low Power Synthesis of Interconnection Networks-on-Chip with Multiple Voltage Islands “, Integration, the VLSI Journal, 45(3):271-281, Jun 2012. |
| J15 | Y. Park, S. Pasricha, F. Kurdahi, N. Dutt, “A Multi-Granularity Power Modeling Methodology for Embedded Processors” , IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 19, No. 4, pp. 668-681, Apr 2011 |
| J14 | Y. Zou, S. Pasricha, “NARCO: Neighbor Aware Turn Model Based Fault Tolerant Routing for NoCs”, IEEE Embedded System Letters, Vol. 2, No. 3, Sep 2010. |
| J13 | S. Pasricha, F. Kurdahi, N. Dutt, “Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 9, pp. 1376-1380, Sep 2010. |
| J12 | S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “CAPPS: A Framework for Power-Performance Trade-Offs in Bus Matrix Based On-Chip Communication Architecture Synthesis”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 18, No. 2, pp. 209-221, Feb 2010. |
| J11 | G. Madl, S. Pasricha, N. Dutt, S. Abdelwahed, “Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs”, IEEE Transactions on Industrial Informatics (TII), Vol. 5, No. 3, Aug 2009 |
| J10 | D. Cho, S. Pasricha, I. Issenin, N. Dutt, Y. Paek , “Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), Vol. 28, No. 4, pp. 554-567, Apr 2009 |
| J9 | S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “System-level PVT Variation Aware Power Exploration of On-Chip Communication Architectures”, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14, No. 2, pp. 20:1-20:25, Mar 2009 |
| J8 | S. Pasricha, N. Dutt, “Trends in Emerging On-Chip Interconnect Technologies”, IPSJ Transactions on System LSI Design Methodology, Vol. 1, Sep 2008 |
| J7 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based Communication Architectures at the CCATB Abstraction”, IEEE Transactions on Embedded Computing Systems (TECS), Feb 2008 |
| J6 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (TCAD), vol.26, no.8, pp.1454-1464, Aug 2007 |
| J5 | S. Pasricha, N. Dutt, “A Framework for Co-synthesis of Memory and Communication Architectures for MPSoC”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 3, pp. 408-420, Mar 2007 |
| J4 | C. Shin, P. Grun, N. Romdhane, C. Lennard, G. Madl, S. Pasricha, N. Dutt, M. Noll, “Enabling Heterogeneous Cycle-Based and Event-Driven Simulation in a SPIRIT-Enabled Design Flow”, Kluwer Journal on Design Automation of Embedded Systems (DAES), Feb 2007 [link] |
| J3 | S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “FABSYN: Floorplan-aware Bus Architecture Synthesis”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol 14, No. 3, pp 241-253, Mar 2006 |
| J2 | S. Pasricha, M. Luthra, S. Mohapatra, N. Dutt, N. Subramanian, “Dynamic Backlight Adaptation for Low Power Handheld Devices”, IEEE Design and Test (D&T), Special Issue on Embedded Systems for Real Time Embedded Systems, Sep-Oct 2004 |
| J1 | S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, N. Subramanian, “Co-optimization of Streaming Multimedia QoS and Backlight Power Consumption for Mobile Handheld Devices”, Special Issue Journal of Korean Multimedia Society (KSSM), Dec 2003 |
Peer Reviewed Conference Papers
| C113 | K. Yao, Y. Ye, S. Pasricha, J. Xu, “Thermal-Sensitive Design and Power Optimization for a 3D Torus-Based Optical NoC,” to appear, IEEE/ACM International Conference on Computer Aided Design (ICCAD), Nov 2017. |
| C112 | V. K. Kukkala, S. Pasricha, T. Bradley, “JAMS: Jitter-Aware Message Scheduling for FlexRay Automotive Networks,” to appear, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2017. |
| C111 | S. Tiku, S. Pasricha, “Energy-Efficient and Robust Middleware Prototyping for Smart Mobile Computing,” to appear, IEEE International Symposium on Rapid System Prototyping (RSP), Oct 2017. |
| C110 | I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling,” to appear, IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Oct 2017. |
| C109 | S. Pasricha, J. Doppa, K. Chakrabarty, S. Tiku, D. Dauwe, S. Jin, P. Pande, “Data Analytics Enables Energy-Efficiency and Robustness: From Mobile to Manycores, Datacenters, and Networks”, to appear, ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2017. |
| C108 | S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing,” ACM System Level Interconnect Prediction Workshop (SLIP), Jun 2017. |
| C107 | H. Mahajan, T. Bradley, S. Pasricha, “Application of STPA to a lane keeping assist system”, Workshop on Systems Approach to Safety and Security (STPA/STAMP), 2017. |
| C106 | V. K. Kukkala, T. Bradley, S. Pasricha, “Uncertainty Analysis and Propagation for an Auxiliary Power Module,” to appear, IEEE Transportation and Electrification Conference (TEC), 2017. |
| C105 | D. Dauwe, S. Pasricha, A. A. Maciejewski, H. J. Siegel, “An Analysis of Resilience Techniques for Exascale Computing Platforms,” 19th Workshop on Advances in Parallel and Distributed Computational Models (APDCM), co-organized with IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2017. |
| C104 | D. Machovec, S. Pasricha, A. A. Maciejewski, H. Jay Siegel, G. A. Koenig, M. Wright, M. Hilton, R. Rambharos, T. Naughton, N. Imam, “Preemptive Resource Management for Dynamically Arriving Tasks in an Oversubscribed Heterogeneous Computing System,” IEEE International Heterogeneity in Computing Workshop (HCW), co-organized with IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2017. |
| C103 | S. Maiti, S. Pasricha, “DELCA: DVFS Efficient Low Cost Multicore Architecture,” ACM Great Lakes Symposium on VLSI (GLSVLSI) , May 2017. |
| C102 | D. Dang, S. V. R. Chittamuru, R. N. Mahapatra, S. Pasricha, “Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs,” IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC), Jan 2017. |
| C101 | I. Thakkar, S. Pasricha, “DyPhase: A Dynamic Phase Change Memory Architecture with Symmetric Write Latency,” IEEE International Conference on VLSI Design (VLSID), Jan 2017. |
| C100 | Y. Biran, S. Pasricha, G. Collins, J. Dubow, “Enabling Green Content Distribution Network by Cloud Orchestration,” 3rd IEEE Smart Cloud Networks & Systems Conference, Dec 2016. (Best Paper Award Candidate) |
| C99 | D. Dauwe, S. Pasricha, A. A. Maciejewski, H. J. Siegel, “A Performance and Energy Comparison of Fault Tolerence Techniques for Exascale Computing Systems,” 6th IEEE International Symposium on Cloud and Service Computing (SC-2), Dec 2016. |
| C98 | V. Y. Raparti, S. Pasricha, “CHARM: A Checkpoint-based Resource Management Framework for Reliable Multicore Computing in the Dark Silicon Era,” IEEE International Conference on Computer Design (ICCD), Oct 2016. |
| C97 | I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2016. |
| C96 | V. Y. Raparti, S. Pasricha, “A Cross-Layer Runtime Framework for Checkpoint-based Soft-Error and Aging Management in SoCs,” SRC Techcon, Sep 2016. |
| C95 | M. Oxley, S. Pasricha, T. Maciejewski, H.J. Siegel and P. Burns, “Online Resource Management in Thermal and Energy Constrained Heterogeneous High Performance Computing,” IEEE International Conference on Big Data Intelligence and Computing (DataCom), Aug 2016. |
| C94 | I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects,” ACM/IEEE System Level Interconnect Prediction Workshop (SLIP), Jun 2016. (Best Paper Award) |
| C93 | I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug 2016. |
| C92 | D. Machovec, B. Khemka, S. Pasricha, A. A. Maciejewski, H. Jay Siegel, G. A. Koenig, M. Wright, M. Hilton, R. Rambharos, N. Imam, “Dynamic Resource Management for Parallel Tasks in an Oversubscribed Energy-Constrained Heterogeneous Environment,” International Heterogeneity in Computing Workshop (HCW) co-located with IEEE International Parallel & Distributed Processing Symposium IPDPS, May 2016. |
| C91 | S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs ,” IEEE/ACM Design Automation Conference (DAC), Jun. 2016. |
| C90 | V. Y. Raparti, S. Pasricha, “Memory-Aware Circuit Overlay NoCs for Latency Optimized GPGPU Architectures,” IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2016. |
| C89 | S. V. R. Chittamuru, I. Thakkar, S. Pasricha, “Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures,” IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2016. (Best Paper Award Candidate) |
| C88 | P. Pande, S. Pasricha, H, Matsutani, “The Future of NoCs: New Technologies and Architectures,” IEEE International Conference on VLSI Design (VLSI), Jan 2016. |
| C87 | I. Thakkar, S. Pasricha, “Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures,” IEEE International Conference on VLSI Design (VLSI), Jan 2016. |
| C86 | S. V. R. Chittamuru, S. Pasricha, “SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip,” IEEE International Conference on VLSI Design (VLSI), Jan 2016. |
| C85 | E. Jonardi, M. Oxley, S. Pasricha, H. J. Siegel and T. Maciejewski, “Energy Cost Optimization for Geographically Distributed Heterogeneous Data Centers,” IEEE Workshop on Energy-efficient Networks of Computers (E2NC): from the Chip to the Cloud, Dec 2015. |
| C84 | S. Pasricha, “Integrated Photonics in Future Multicore Computing: New Directions in Dependability and Power Efficiency,” IEEE Second Workshop on Low-Power Dependable Computing (LPDC), Dec 2015. (Invited Keynote Paper) |
| C83 | I. Thakkar, S. Pasricha, “A Novel 3D Graphics DRAM Architecture for High-Performance and Low-Energy Memory Accesses,” IEEE International Conference on Computer Design (ICCD), Oct 2015. |
| C82 | V. K. Kukkala, T. Bradley, S. Pasricha, “Priority-based Multi-level Monitoring of Signal Integrity in a Distributed Powertrain Control System,” 4th IFAC Workshop on Engine and Powertrain Control, Simulation and Modeling, Jul 2015. (Invited) |
| C81 | S. Pasricha, V. Ugave, Q. Han and C. Anderson, “LearnLoc: A Framework for Smart Indoor Localization with Embedded Mobile Devices,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2015. |
| C80 | N. Kapadia, V. Y. Raparti, S. Pasricha, “ARTEMIS: An Aging-Aware Run-Time Application Mapping Framework for 3D NoC based Chip Multiprocessors,” IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2015. |
| C79 | B. Khemka, R. Friese, S. Pasricha, A. A. Maciejewski, H. J. Siegel, G. A. Koenig, S. Powers, M. Hilton, R. Rambharos, M. Wright, S. Poole, “Comparison of Energy-Constrained Resource Allocation Heuristics Under Different Task Management Environments,” International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2015. |
| C78 | S. Maiti, N. Kapadia, S. Pasricha, “Process Variation Aware Dynamic Power Management in Multicore Systems with Extended Range Voltage/Frequency Scaling,” IEEE MWSCAS 2015. |
| C77 | S. V. R. Chittamuru, S. Pasricha, “Improving Crosstalk Resilience with Wavelength Spacing in Photonic Crossbar-based Network-on-Chip Architectures,” IEEE MWSCAS 2015. |
| C76 | N. Kapadia, S. Pasricha, “Process-Variation and Soft-Error Reliability-Aware Workload Mapping with Adaptive Parallelism in SoCs ,” SRC Techcon, 2015. |
| C75 | D. Dauwe, E. Jonardi, R. Friese, S. Pasricha, A. A. Maciejewski, D. Bader, H.J. Siegel, “A Methodology for Co-Location Aware Application Performance Modeling in Multicore Computing,” 17th Workshop on Workshop on Advances in Parallel and Distributed Computational Models (APDCM), May 2015. |
| C74 | S. V. R. Chittamuru, S. Desai, S. Pasricha, “A Reconfigurable Silicon-Photonic Network with Improved Channel Sharing for Multicore Architectures,” ACM GLSVLSI, May 2015. (Best Paper Award) |
| C73 | N. Kapadia, S. Pasricha, “VARSHA: Variation and Reliability-Aware Application Scheduling with Adaptive Parallelism in the Dark-Silicon Era,” IEEE/ACM Design Automation & Test in Europe (DATE), Mar 2015. |
| C72 | S. Pasricha, I. Thakkar, “Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces”, Memory Architecture and Organization Workshop (MeAOW), Oct 2014 (Invited) |
| C71 | N. Kapadia, S. Pasricha, “PRATHAM: A Power Delivery-Aware and Thermal-Aware Mapping Framework for Parallel Embedded Applications on 3D MPSoCs,” IEEE International Conference on Computer Design (ICCD), Oct 2014 |
| C70 | I. Thakkar, S. Pasricha, “3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time,” IEEE International Conference on Computer Design (ICCD), Oct 2014. |
| C69 | Y. Zou, S. Pasricha, “HEFT: A Hybrid System-Level Framework for Enabling Energy-Efficient Fault-Tolerance in NoC based MPSoCs,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2014. |
| C68 | Y. Xiang, S. Pasricha, “Fault-Aware Application Scheduling in Low Power Embedded Systems with Energy Harvesting,” ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct 2014. |
| C67 | M. Oxley, E. Jonardi, S. Pasricha, A. A. Maciejewski, G. Koenig and H. J. Siegel “Thermal, Power, and Co-location Aware Resource Allocation in Heterogeneous Computing Systems,” IEEE International Green Computing Conference (IGCC), 2014. |
| C66 | D. Dauwe, R. Friese, S. Pasricha, A. A. Maciejewski, G. A. Koenig, H. J. Siegel, ” Modeling the Effects on Power and Performance from Memory Interference of Co-located Applications in Multicore Systems,” International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), 2014. |
| C65 | H. J. Siegel, B. Khemka, R. Friese, S. Pasricha, A. A. Maciejewski, G. A. Koenig, S. Powers, M. Hilton, J. Rambharos, G. Okonski, and S. W. Poole, “Energy-Aware Resource Management for Computing Systems,” 7th International Conference on Contemporary Computing (IC3), Noida, India, Aug. 2014. |
| C64 | B. Khemka, G. A. Koenigz, R, Friese, S. Powers, S. Pasricha, A. A. Maciejewski, M. Hilton, R. Rambharos, H. J. Siegel, S. Poole, “Utility Driven Dynamic Resource Management in an Oversubscribed Energy-Constrained Heterogeneous System”, 23rd International Heterogeneity in Computing Workshop (HCW), May 2014. |
| C63 | Y. Xiang, S. Pasricha, “A Hybrid Framework for Application Allocation and Scheduling in Multicore Systems with Energy Harvesting”, ACM Great Lakes Symposium on VLSI (GLSVLSI), May. 2014. |
| C62 | D. Jaramillo, V. Ugave, R. Smart, S. Pasricha, “A Secure Cross-Platform Hybrid Mobile Enterprise Voice Agent,” IEEE SoutheastCon, Mar 2014. |
| C61 | S. Bahirat, S. Pasricha, “HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific Network-On-Chip Architectures ”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2014. |
| C60 | T. Pimpalkhute, S. Pasricha, “An Application-Aware Heterogeneous Prioritization Framework for NoC based Chip Multiprocessors”, IEEE International Symposium on Quality Electronic Design (ISQED), Mar. 2014. |
| C59 | S. Bahirat, S. Pasricha, “3D HELIX: Design and Synthesis of Hybrid Nanophotonic Application-Specific 3D Network-On-Chip Architectures ”, Workshop on Exploiting Silicon Photonics for Energy efficient Heterogeneous Parallel Architectures (SiPhotonics), Jan. 2014. |
| C58 | T. Pimpalkhute, S. Pasricha, “NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-Core Systems”, IEEE International Conference on VLSI Design (VLSID), Jan. 2014. |
| C57 | N. Kapadia, S. Pasricha, “Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize Yield”, IEEE International Conference on VLSI Design (VLSID), Jan. 2014. |
| C56 | M. Oxley, S. Pasricha, H. J. Siegel, and A. Maciejewski, “Energy and Deadline Constrained Robust Stochastic Static Resource Allocation”, Workshop on Power and Energy Aspects of Computation (PEAC) held in conjunction with the 10th International Conference on Parallel Processing and Applied Mathematics (PPAM), Sep. 2013. |
| C55 | R. Friese, T. Brinks, C. Oliver, A. Maciejewski, H. J. Siegel, S. Pasricha, “A Machine-by-Machine Analysis of a Bi-Objective Resource Allocation Problem”, International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA), Jul. 2013. |
| C54 | D. Young, J. Smith, S. Pasricha, A. Maciejewski and H. J. Siegel, “Heterogeneous Energy and Makespan Constrained DAG Scheduling”, International Workshop on Energy Efficient High Performance Parallel and Distributed Computing (EEHPDC), Jun. 2013. |
| C53 | Y. Xiang, S. Pasricha, “Harvesting-Aware Energy Management for Multicore Platforms with Hybrid Energy Storage ”, ACM Great Lakes Symposium on VLSI (GLSVLSI 2013), May 2013. |
| C52 | N. Kapadia, S. Pasricha, “A Co-Synthesis Methodology for Power Delivery and Data Interconnection Networks in 3D ICs”, IEEE International Symposium on Quality Electronic Design (ISQED 2013), Mar. 2013. |
| C51 | N. Kapadia, S. Pasricha, “VERVE: A Framework for Variation-Aware Energy Efficient Synthesis of NoC-based MPSoCs with Voltage Islands”, IEEE International Symposium on Quality Electronic Design (ISQED 2013), Mar. 2013. |
| C50 | Y. Zou, S. Pasricha, “Reliability-Aware and Energy-Efficient Synthesis of NoC based MPSoCs”, IEEE International Symposium on Quality Electronic Design (ISQED 2013), Mar. 2013. |
| C49 | Y. Xiang, S. Pasricha, “Thermal-Aware Semi-Dynamic Power Management for Multicore Systems with Energy Harvesting”, IEEE International Symposium on Quality Electronic Design (ISQED 2013), Mar. 2013. |
| C48 | M. Salas, S. Pasricha, “The Roce-Bush Router: A Case for Routing-centric Dimensional Decomposition for Low-latency 3D NoC Routers”, ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2012), Oct 2012. |
| C47 | A. M. Al-Qawasmeh, S. Pasricha, A. M. Maciejewski, and H. J. Siegel, “Thermal-Aware Performance Optimization in Power Constrained Heterogeneous Data Centers”, 21st International Heterogeneity in Computing Workshop (HCW 2012), 2012. |
| C46 | B. Donohoo, C. Ohlsen, S. Pasricha, C. Anderson, “Exploiting Spatiotemporal and Device Contexts for Energy-Efficient Mobile Embedded Systems”, IEEE/ACM Design Automation Conference (DAC 2012), Jul. 2012. |
| C45 | S. Bahirat, S. Pasricha, “A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip”, IEEE International Symposium on Quality Electronic Design (ISQED 2012), Mar. 2012. |
| C44 | N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands”, IEEE International Conference on VLSI Design (VLSID 2012), Jan. 2012. |
| C43 | S. Pasricha, “A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip”, IEEE International Conference on VLSI Design (VLSID 2012), Jan. 2012. |
| C42 | Y. Zou, Y. Xiang, S. Pasricha, “Analysis of On-chip Interconnection Network Interface Reliability in Multicore Systems”, IEEE International Conference on Computer Design (ICCD 2011), Oct. 2011. |
| C41 | B. Donohoo, C. Ohlsen, S. Pasricha, “AURA: An Application and User Interaction Aware Middleware Framework for Energy Optimization in Mobile Devices”, IEEE International Conference on Computer Design (ICCD 2011), Oct. 2011. |
| C40 | D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, Fourth International Workshop on Parallel Programming Models and Systems Software for High-End Computing (P2S2 2011), Sep 2011. |
| C39 | J. Apodaca, D. Young, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Stochastically Robust Static Resource Allocation for Energy Minimization with a Makespan Constraint in a Heterogeneous Computing Environment”, ACS/IEEE International Conference on Computer Systems and Applications (AICCSA 2011), Dec 2011. (Best Paper Award) |
| C38 | N. Kapadia, S. Pasricha, “VISION: A Framework for Voltage Island Aware Synthesis of Interconnection Networks-on-Chip”, ACM Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland, May 2011. |
| C37 | S. Pasricha, Y. Zou, “A Low Overhead Fault Tolerant Routing Scheme for 3D Networks-on-Chip”, IEEE International Symposium on Quality Electronic Design (ISQED 2011) , Santa Clara, CA, Mar 2011 |
| C36 | S. Kwon, S. Pasricha, “POSEIDON: A Framework for Application-Specific Network-on-Chip Synthesis for Heterogeneous Chip Multiprocessors”, IEEE International Symposium on Quality Electronic Design (ISQED 2011), Santa Clara, CA, Mar 2011 |
| C35 | S. Pasricha, Y. Zou, “NS-FTR: A Fault Tolerant Routing Scheme for Networks on Chip with Permanent and Runtime Intermittent Faults”, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC 2011), Yokohama, Japan, Jan 2011 |
| C34 | S. Pasricha, S. Bahirat, “OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs”, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC 2011), Yokohama, Japan, Jan 2011 |
| C33 | S. Pasricha, Y. Zou, D. Connors, H. J. Siegel, “OE+IOE: A Novel Turn Model Based Fault Tolerant Routing Scheme for Networks-on-Chip”, Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2010),Scottsdale, AZ, Oct 2010 |
| C32 | S. Pasricha, “Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors”, 21st Annual Workshop on Interconnections within High Speed Digital Systems (HSD 2010), Santa Fe, New Mexico, May 2010 (Invited) |
| C31 | S. Bahirat, S. Pasricha, “UC-PHOTON: A Novel Hybrid Photonic Network-on-Chip for Multiple Use-Case Applications”, IEEE International Symposium on Quality Electronic Design (ISQED 2010) Santa Clara, CA, Mar 2010 (Best Paper Award) |
| C30 | L. A. D. Bathen, Y. Ahn, S. Pasricha, N. Dutt, “A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations”, IEEE International Workshop on Microprocessor Test and Verification (MTV 2009), Austin, TX, Dec 2009 |
| C29 | L. A. D. Bathen, Y. Ahn, N. Dutt, S. Pasricha, “Inter-kernel Data Reuse and Pipelining on Chip-Multiprocessors for Multimedia Applications”, IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2009) Grenoble, France, Oct 2009 |
| C28 | S. Bahirat, S. Pasricha, “Exploring Hybrid Photonic Networks-on-Chip for Emerging Chip Multiprocessors”, IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2009), Grenoble, France, Oct 2009 |
| C27 | S. Pasricha, “Exploring Serial Vertical Interconnects for 3D ICs”, IEEE/ACM Design Automation Conference (DAC 2009), San Francisco, CA, Jul 2009 |
| C26 | R. Kost, D. Connors, S. Pasricha, “Characterizing the Use of Program Vulnerability Factors for Studying Transient Fault Tolerance in Multi-core Architectures”, Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS 2009) Estoril, Portugal, Jun 2009 |
| C25 | A. Gupta, S. Pasricha, N. Dutt, F. Kurdahi, K. Khouri, M. Abadir, “On-Chip Communication Architecture Based Thermal Management for SoCs”, IEEE VLSI Design, Automation & Test (VLSI-DAT 2009), Hsinchu, Taiwan, Apr 2009 |
| C24 | S. Pasricha, N. Dutt, F. Kurdahi, “Dynamically Reconfigurable On-Chip Communication Architectures for Multi Use-Case Chip Multiprocessor Applications”, IEEE/ACM Asia & South Pacific Design Automation Conference (ASPDAC 2009), Yokohama, Japan, Jan 2009 |
| C23 | S. Pasricha, F. Kurdahi, N. Dutt, “Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications”,IEEE VLSI Design Conference (VLSID 2009), New Delhi, India, Jan 2009 |
| C22 | L. A. D. Bathen, N. Dutt, S. Pasricha, “A Framework for Memory-aware Multimedia Application Mapping on Chip-Multiprocessors”,IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2008), Atlanta, GA, Oct 2008 |
| C21 | Y. Park, S. Pasricha, F. Kurdahi, N. Dutt, ” Methodology for Multi-Granularity Embedded Processor Power Model Generation for an ESL Design Flow”, IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2008), Atlanta, GA, Oct 2008 |
| C20 | S. Pasricha, F. Kurdahi, N. Dutt, ” System Level Performance Analysis of Carbon Nanotube Global Interconnects for Emerging Chip Multiprocessors”, IEEE/ACM International Symposium on Nanoscale Architectures, (NanoArch 2008), Anaheim, CA, Jun 2008 |
| C19 | H. Homayoun, S. Pasricha, M. Makhzan, A. Veidenbaum, “Dynamic Register File Resizing to Improve Embedded Processor Performance and Energy-delay Efficiency”, IEEE/ACM Design and Automation Conference (DAC 2008), Anaheim, CA, Jun 2008 |
| C18 | D. Cho, S. Pasricha, I. Issenin, N. Dutt and Y. Paek, “Compiler Driven Data Layout Optimization for Regular/Irregular Array Access Patterns”, ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2008), Tucson, AZ, Jun 2008 |
| C17 | H. Homayoun, S. Pasricha, M. Makhzan, A. Veidenbaum, ” Improving Performance and Reducing Energy-Delay with Adaptive Resource Resizing for Out-of-Order Embedded Processors ”, ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES 2008), Tucson, AZ, Jun 2008 |
| C16 | S. Pasricha, Y. Park, S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, ” Incorporating PVT Variations in System-level Power Exploration of On-Chip Communication Architectures”, IEEE VLSI Design Conference (VLSID 2008), Bangalore, India, Jan 2008 |
| C15 | S. Pasricha, N. Dutt, “ORB: An On-chip Optical Ring Bus Communication Architecture for Multi-Processor Systems-on-Chip”, IEEEAsia & South Pacific Design Automation Conference (ASPDAC 2008), Seoul, Korea, Jan 2008 |
| C14 | Y. Park, S. Pasricha, F. Kurdahi, N. Dutt, “System Level Power Estimation Methodology with H.264 Decoder Prediction IP Case Study”, IEEE International Conference on Computer Design (ICCD 2007), Great Lakes, CA, Oct 2007 |
| C13 | S. Pasricha, N. Dutt, “On-chip Communication Architecture Synthesis for High Performance MPSoCs”, SRC TechConnect, Nov 2007 |
| C12 | S. Pasricha, Y. Park, F. Kurdahi, N. Dutt, “System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis”, IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2006), Seoul, Korea, Oct 2006 |
| C11 | G. Madl, S. Pasricha, Q. Zhu, L. Bathen, N. Dutt, “Formal Performance Evaluation of AMBA-based System-on-Chip Designs”, 6th Annual ACM Conference on Embedded Software (EMSOFT 2006), Seoul, Korea, Oct 2006 |
| C10 | S. Pasricha, N. Dutt, “COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC”,IEEE/ACM Design Automation and Test in Europe Conference (DATE 2006), Munich, Germany, Mar 2006 |
| C9 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Constraint-Driven Bus Matrix Synthesis for MPSoC”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC 2006), Yokohama, Japan, Jan 2006 (Best Paper Award) |
| C8 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Using TLM for Exploring Bus-based SoC Communication Architectures”, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2005), Samos, Greece, Jul 2005(invited paper) |
| C7 | S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “Floorplan-aware Automated Synthesis of Bus-based Communication Architectures”, IEEE/ACM Design and Automation Conference (DAC 2005), Anaheim, CA, Jun 2005 (Best Paper Candidate) |
| C6 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Automated Throughput-driven Synthesis of Bus-based Communication Architectures”, Asia and South Pacific Design Automation Conference (ASPDAC 2005), Shanghai, China, Jan 2005 |
| C5 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based On-chip Communication Architectures”, International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004), Stockholm, Sweden, Sep 2004 |
| C4 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration”, Design and Automation Conference (DAC 2004), San Diego, CA, Jun 2004 |
| C3 | S. Pasricha, S. Mohapatra, M. Luthra, N. Dutt, N. Subramanian, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices”, Embedded Systems for Real-Time Multimedia (ESTIMedia 2003), Newport Beach, CA,Oct 2003 |
| C2 | S. Pasricha, A. Veidenbaum, “Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches” International Conference on Computer Design (ICCD 2003), San Jose, CA, Oct 2003 |
| C1 | S. Pasricha, “Transaction Level Modeling of SoC with SystemC 2.0” Synopsys User Group Conference (SNUG 2002), Bangalore, May 2002 |
Guest Editorials
| GE1 | Y. Xu, S. Pasricha, “Guest Editor’s Introduction: Special Issue on Silicon Nanophotonics for Future Multicore Architectures”, IEEE Design and Test (IEEE D&T), Sep/Oct 2014. |
Patents
| PAT1 | S. Pasricha, N. Dutt, M. Ben Romdhane, “Method for the fast exploration of bus-based communication architectures at the cycle-count-accurate-at-transaction-boundaries (CCATB) abstraction”, Patent number 7,778,815, Aug. 2010 |
Invited Workshop Papers and Posters
| W9 | S. Pasricha, “Cross-layer Fault Resilience for Silicon Photonic Interconnection Networks”, International Workshop on Cross-Layer Resilience (IWCR), Jul 2016. |
| W8 | S. Pasricha, I. Thakkar, “Re-architecting DRAM memory systems with 3D Integration and Photonic Interfaces”, Memory Architecture and Organization Workshop (MeAOW), Oct 2014. |
| W7 | S. Pasricha, “Enabling Cross-layer Fault Resilience for On-Chip Networks in SoCs,” 2nd NSF/SRC/DFG International Workshop on Cross-Layer Resilience (IWCR), Jul 2014. |
| W6 | M. Oxley, S. Pasricha, H. J. Siegel, and A. A. Maciejewski, “Stochastic-Based Deadline-Aware and Energy-Constrained Robust Static Resource Management,” Workshop on Algorithms and Scheduling Techniques for Exascale Systems, sponsor: Schloss Dagstuhl – Leibniz Center for Informatics, Wadern, Germany, Sep. 2013. |
| W5 | S. Pasricha, “Enabling Fault Resilient Interconnection Networks,” NSF/SRC/DFG International Workshop on Cross-Layer Resilience (IWCR), Jul 2013 |
| W4 | S. Pasricha, “Design Automation Challenges at the Extreme Scale: A System Level Perspective,” NSF/CCC Workshop for Extreme Scale Design Automation (ESDA), Jun 2013 |
| W3 | S. Pasricha, “Design Automation for Emerging Technologies: An Interconnect Perspective,” NSF/CCC Workshop for Extreme Scale Design Automation (ESDA), Jun 2013. |
| W2 | S. Pasricha, S. Bahirat, “Design and Exploration of the PHOTON Hybrid Nanophotonic-electric On-chip Communication Architecture”, IEEE CANDE Workshop, Oct. 2009. |
| W1 | S. Pasricha, “Customizing Memories for MPSoCs”, Workshop on Compiler-Assisted System-On-Chip Assembly (CASA), Oct. 2009. |
Conference Tutorials
| TU5 | A. T-Sanial, S. Pasricha, P. Pande, K. Chakrabarty, “3D Integration: Quo Vadis?” Full day tutorial at IEEE Design Automation and Test in Europe Conference, (DATE), Mar 2017. |
| TU4 | S. Pasricha, N. Dutt, L. Benini, “On-Chip Communication Architectures: Buses, Networks-on-Chip, and Beyond ”, Full day tutorial at 41st IEEE/ACM International Symposium on Microarchitecture (MICRO 2008), Lake Como, Italy, Nov 2008 |
| TU3 | S. Pasricha, K. Lahiri, and N. Dutt, “Modeling, Analysis and Design of Bus-based SOC Communication Architectures”, Half day tutorial at IEEE Design Automation and Test in Europe, (DATE 2007), Nice, France, Apr 2007 |
| TU2 | S. Pasricha, K. Banerjee, L. Benini, K. Lahiri and N. Dutt, “SoC Communication Architectures: Technology, Current Practice, Research and Trends”, Full day tutorial at IEEE VLSI Design Conference (VLSID 2007), Bangalore, India, Jan 2007 |
| TU1 | S. Pasricha, N. Dutt, “SoC Communication Architectures: Current Practice, Research and Trends”, Half day tutorial at the Asia and South Pacific Design Automation Conference (ASPDAC 2006), Yokohama, Japan, Jan 2006 |
Posters
| P15 | H. Mahajan, T. Bradley, S. Pasricha, “Engineering Safer Systems in an Increasingly Complex World”, Colorado State University Graduate Student Showcase, Nov. 2016. |
| P14 | S. V. R. Chittamuru, S. Pasricha, “Cross-Layer Framework for Reliable and Energy-Efficient Silicon Photonic NoC Design for Future Many-Core Architectures”, ACM/IEEE Design Automation Conference SIGDA Ph.D. forum, Jun. 2016. |
| P13 | I. Thakkar, S. V. R. Chittamuru, S. Pasricha, “A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects”, ACM/IEEE Design Automation Conference Work in Progress (WIP), Jun. 2016. |
| P12 | S. V. R. Chittamuru, S. Pasricha, “Overcoming Data Movement Barriers in Future Many Core Chips with Silicon Nanophotonics”, CSU Ventures Innovation Forum, Apr 2016. |
| P11 | I. Thakkar, S. Pasricha, “Improving the Performance and Power Efficiency of Memory with 3D Stacking and High-Bandwidth Optical Interfacing”, CSU Ventures Innovation Forum, Apr 2016. |
| P10 | D. Dauwe, S. Pasricha, “Overcoming Resource Failures and Sharing Conflicts in Large-scale Datacenters and Supercomputers”, CSU Ventures Innovation Forum, Apr 2016. |
| P9 | V. K. Kukkala, S. Pasricha, “JAMS: Jitter Aware Message Scheduling for FlexRay Automotive Networks”, CSU Ventures Innovation Forum, Apr 2016. |
| P8 | S. Bahirat, S. Pasricha, “Design and Synthesis of Hybrid Nanophotonic NoCs for Future Many-Core Architectures”, ACM/IEEE Design Automation Conference SIGDA Ph.D. forum, Jun. 2013. |
| P7 | N. Kapadia, S. Pasricha, “A Holistic Framework for Multi-objective Synthesis of 2D and 3D NoC-based MPSoCs with Voltage Islands”, ACM/IEEE Design Automation Conference SIGDA Ph.D. forum, Jun. 2013. |
| P6 | N. Kapadia, S. Pasricha, “A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip”, IEEE Computer-Aided Network DEsign CANDE Workshop, Oct. 2011. |
| P5 | D. Young, J. Apodaca, L. Briceno, J. Smith, S. Pasricha, A. Maciejewski, H. Siegel, S. Bahirat, B. Khemka, A. Ramirez and Y. Zou, “Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment”, FRCRC First Annual Front Range High Performance Computing Symposium, Oct. 2011. (Winner of Best Poster Award) |
| P4 | S. Bahirat, S. Pasricha, “Design and Exploration of the PHOTON Hybrid Nanophotonic-electric On-chip Communication Architecture”, IEEE CANDE Workshop, Oct 2009. |
| P3 | S. Pasricha, “COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor System-on-Chips”, ICS Seminar, May 2007 |
| P2 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Fast Exploration of Bus-based Communication Architectures”, CECS ISLPD Open House 2004, Irvine, CA, Aug 2004 |
| P1 | S. Pasricha et al, “Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices”, Southern California Embedded Systems Symposium (SCESS) 2003, Irvine, CA, Sep 2003 (Winner of 2nd Place SCESS Best Poster Award) |
Thesis
| TH1 | S. Pasricha, “COMMSYN: On-Chip Communication Architecture Synthesis for Multi-Processor Systems-on-Chip ”, Ph.D. Thesis, University of California, Irvine, Jun 2008 |
(Old) Technical Reports
| TR9 | S. Pasricha, Y. Park, F. Kurdahi and N. Dutt, “Power-Performance Trade-Offs for Bus Matrix Communication Architectures”, CECS Technical Report 06-12, Nov 2006 |
| TR8 | S. Pasricha, N. Dutt, “A Framework for Memory and Communication Architecture Co-synthesis in MPSoCs,” CECS Technical Report 06-03, Feb 2006 |
| TR7 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Bus Matrix Communication Architecture Synthesis,” CECS Technical Report 05-13, Oct 2005 |
| TR6 | S. Pasricha, N. Dutt, E. Bozorgzadeh, M. Ben-Romdhane, “Floorplan-aware Bus Architecture Synthesis,” CECS Technical Report 04-27, Oct 2004 |
| TR5 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Automated Synthesis of Bus Architectures for Systems with Throughput Constraints”, CECS Technical Report 04-20, Aug 2004 |
| TR4 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “Rapid Exploration of Bus-based Communication Architectures at the CCATB Abstraction”, CECS Technical Report 04-11, May 2004 |
| TR3 | S. Pasricha, N. Dutt, M. Ben-Romdhane, “High Level Design Space Exploration of Shared Bus Communication Architectures”, CECS Technical Report 04-06, Mar 2004 |
| TR2 | S. Pasricha, A. Veidenbaum, “Novel Techniques to Improve Branch Prediction Accuracy for Embedded Processors in the Presence of Context Switches”, CECS Technical Report 03-24, Aug 2003 |
| TR1 | S. Pasricha, P. Mishra, P. Biswas, A. Shrivastava, A. Mandal, N. Dutt, A. Nicolau, “A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor”, CECS Technical Report 03-17, Apr 2003 |
User Manuals
| U1 | P. Biswas, S. Pasricha, P. Mishra, A. Shrivastava, A. Nicolau, N. Dutt “EXPRESSION User Manual Version 1.0” |