ECE554: Lectures

• Chapter 1 (H&P)
• A. J. Smith, “The Task of the Referee,” IEEE Computer 1990.
• G. Amdahl “Validity of the single processor approach to achieving large scale computing capabilities,” AFIPS Conference, April 1967.
• G. Moore, “Cramming more components onto integrated circuits,” Electronics, April 1965.

• Appendix A, B, C (H&P)
• R. Ronen et al., “Coming Challenges in Microarchitecture and Architecture,” IEEE, vol. 89, no. 11, 2001.
• Y. Patt, “Requirements, bottlenecks, and good fortune: agents for microprocessor evolution,” IEEE, vol. 89, no. 11, 2001.
• R. P. Colwell et al., “Instruction Sets and Beyond: Computers, Complexity, and Controversy,” 1985.
• D. Patterson, J. Hennessy, “Response to ‘Computers, Complexity, and Controversy’,” 1985.
• R. P. Colwell, “More controversy about ‘Computers, Complexity, and Controversy’,” 1985.

• Chapter 2 (H&P)
• N. Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,” ISCA, 1990
• N. Hardavellas et al.,  “Reactive NUCA: near-optimal block placement and replication in distributed caches,”  ISCA, 2009.

• Chapter 2 (H&P)
• D. Burger et al., “Memory Bandwidth Limitations of Future Microprocessors,”  , ISCA 1996.
• H. Yoon et al., “Row Buffer Locality-Aware Data Placement in Hybrid Memories,” TechReport CMU, 2011.

Homework Assignment 1

• Chapter 3 (H&P)
• D. Sima, “The design space of register renaming techniques”, IEEE MICRO, 2000.
• E. Sprangle et al, “Increasing Processor Performance by Implementing Deeper Pipelines,” ISCA, 2002.

Homework Assignment 2

• Chapter 3 (H&P)
• E. Rotenberg et al., “Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching”, MICRO-29, 1996.
• M. Moudgill et al., “Precise Interrupts”, MICRO, 1996.

• Chapter 4 (H&P)
• V. W. Lee et al., “Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU,” ISCA 2010

Homework Assignment 3

• Chapter 5 (H&P)
• J. Zebchuk et al., “A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy,”  MICRO, 2007.

• R. Hammed et al., “ Application-specific processors: “Understanding Sources of Inefficiency in General-Purpose Chips,”  ISCA, 2010.

• Chapter 6 (H&P) K. Lim et al., “Server Designs for Warehouse-Computing Environments,” MICOR, 2009.